The semiconductor industry is continually striving to fabricate integrated circuits with ever increasing performance and higher packing densities. Traditionally, the semiconductor industry has simultaneously met both the performance and the packing density requirements by reducing the feature size of semiconductor devices. As the feature size of semiconductor devices continues to be reduced, however, gains in integrated circuit performance, that are normally associated with a reduction in device feature size, are less than expected. This occurs because as device dimensions are reduced other effects, such as parasitic capacitance, are no longer negligible and increases in integrated circuit performance, resulting from a reduction in device feature size, are limited by parasitic capacitance. Therefore, the parasitic capacitance associated with semiconductor devices must be minimized in order to achieve integrated circuits with improved performance. Accordingly, a need exists for semiconductor devices with reduced parasitic capacitance.